? semiconductor components industries, llc, 2016 february, 2016 ? rev. p0 1 publication order number: NCP81155/d NCP81155 product preview mosfet driver the NCP81155 is a high?performance dual mosfet gate driver in a small 3 mm x 3 mm package, optimized to drive the gates of both high?side and low?side power mosfets in a buck or buck?boost application. vcc uvlo ensures the mosfets are off when supply voltages are low. a bi?directional enable pin provides a fault signal to the controller when a uvlo fault is detected. features ? space?efficient 3 mm x 3 mm dfn8 thermally?enhanced package ? vcc range of 4.5 v to 13.2 v ? integrated bootstrap diode ? compatible with 3.3 v and 5 v pwm inputs ? bi?directional enable feature pulls enable pin low during a uvlo fault. ? adaptive anti?cross conduction circuit protects against cross?conduction during fet turn?on and turn?off ? output disable control turns off both mosfets ? vcc undervoltage lockout ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? e?cigarettes ? unmanned aerial vehicles (uav) this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. device package shipping ? ordering information www. onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. dfn8 mn suffix case 506bj marking diagram NCP81155mntwg dfn8 (pb?free) 3000 / tape & ree l 1 81155 = specific device code a = assembly location l = wafer lot y = year w = work week = pb?free package 81155 alyw 1 (note: microdot may be in either location) drvh sw gnd drvl bst pwm en vcc 1 flag (top view) 9 pin connections 8 27 36 45
NCP81155 www. onsemi.com 2 bst pwm logic drvh sw anti?cross conduction vcc drvl vcc en fault uvlo vcc figure 1. simplified block diagram table 1. pin descriptions pin no. symbol description 1 bst floating bootstrap supply pin for high side gate driver. connect the bootstrap capacitor between this pin and the sw pin. 2 pwm control input: pwm = high ? drvh is high, drvl is low. pwm = low ? drvh is low, drvl is high. 3 en enable input: en = high ? driver is enabled. en = low ? driver is disabled. 4 vcc power supply input. connect a bypass capacitor (0.1 f) from this pin to ground. 5 drvl low side gate drive output. connect to the gate of low side mosfet. 6 gnd bias and reference ground. all signals are referenced to this node (qfn flag). 7 sw switch node. connect this pin to the source of the high side mosfet and drain of the low side mosfet. 8 drvh high side gate drive output. connect to the gate of high side mosfet. 9 flag thermal flag. there is no electrical connection to the ic. connect to ground plane.
NCP81155 www. onsemi.com 3 table 2. absolute maximum ratings rating symbol min max main supply v oltage input (note 1) vcc ?0.3 v 15 v bootstrap supply voltage bst ?0.3 v wrt/sw 35 v wrt/gnd 40 v ( 50 ns) wrt/gnd 15 v wrt/ sw switching node voltage sw ?5 v ?10 v ( 200 ns) 35 v 40 v ( 50 ns) high side driver output drvh ?0.3 v wrt/sw ?2 v ( 200 ns) wrt/sw bst+0.3 v low side driver output drvl ?0.3 v ?5 v ( 200 ns) vcc+0.3 v drvh/drvl control input, enable pin pwm ?0.3 v 6.5 v ground gnd 0 v 0 v storage temperature range t stg ?55 c 150 c operating junction temperature range t j ?40 c 150 c moisture sensitivity level msl 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected. 1. refer to electrical characteristics and application information for safe operating area. table 3. thermal characteristics rating symbol value unit thermal characteristic, dfn8 (note 2) thermal resistance, junction?to?air r ja 55 c/w 2. values based on copper area of 645 mm 2 (or 1 in 2 ) of 1 oz copper thickness and fr4 pcb substrate. table 4. operating ranges (note 3) rating symbol min max unit input v oltage vcc 4.5 13.2 v ambient t emperature t a ?10 125 c 3. refer to electrical characteristics and application information for safe operating area.
NCP81155 www. onsemi.com 4 table 5. electrical characteristics ( unless otherwise stated: ?10 c < t a < +125 c; 4.5 v < v cc < 13.2 v, 4.5 v < bst?swn < 13.2 v, 4.5 v < bst < 30 v, 0 v < swn < 21 v) parameter test conditions min. typ. max. units supply voltage vcc operation voltage 4.5 13.2 v undervoltage lockout vcc start threshold 3.8 4.35 4.5 v vcc uvlo hysteresis 150 200 250 mv supply current normal mode icc + ibst, en = 5 v, pwm = osc, fsw = 100 khz, cload = 3 nf for drvh, 3 nf for drvl 10 ma standby current icc + ibst, en = gnd 0.5 1.4 ma standby current i cc + i bst , en = high, pwm = low, no loading on drvh & drvl 2.0 ma standby current i cc + i bst , en = high, pwm = high, no loading on drvh & drvl 2.0 ma bootstrap diode forward v oltage v cc = 12 v, forward bias current = 2 ma 0.1 0.4 0.6 v pwm input pwm input high 2.0 v pwm input low 0.8 v high side driver (vcc = 12 v) output impedance, sourcing current vbst ? vsw = 12 v 1.9 3.0 output impedance, sinking current vbst ? vsw = 12 v 1.0 1.7 drvh rise time tr drvh v vcc = 12 v, 3 nf load, vbst?vsw = 12 v 16 30 ns drvh fall time tf drvh v vcc = 12 v, 3 nf load, vbst?vsw = 12 v 11 25 ns drvh turn?off propagation delay tpdl drvh c load = 3 nf tbd 13 tbd ns drvh turn?on propagation delay tpdh drvh c load = 3 nf 30 ns drvh pull down resistance drvh to sw, bst?sw = 0 v 37.5 k high side driver (vcc = 5 v) output impedance, sourcing current vbst ? vsw = 5 v 2.5 output impedance, sinking current vbst ? vsw = 5 v 1.6 drvh rise time tr drvh v vcc = 5 v, 3 nf load, vbst ? vsw = 5 v 30 ns drvh fall time tf drvh v vcc = 5 v, 3 nf load, vbst ? vsw = 5 v 27 ns drvh turn?off propagation delay tpdl drvh c load = 3 nf tbd ns drvh turn?on propagation delay tpdh drvh c load = 3 nf 27 ns sw pull down resistance sw to pgnd 37.5 k low side driver (vcc = 12 v) output impedance, sourcing current 2.0 3.0 output impedance, sinking current 0.7 1.5 drvl rise time tr drvl c load = 3 nf 16 35 ns drvl fall time tf drvl c load = 3 nf 11 20 ns
NCP81155 www. onsemi.com 5 table 5. electrical characteristics ( unless otherwise stated: ?10 c < t a < +125 c; 4.5 v < v cc < 13.2 v, 4.5 v < bst?swn < 13.2 v, 4.5 v < bst < 30 v, 0 v < swn < 21 v) parameter units max. typ. min. test conditions low side driver (vcc = 12 v) drvl turn?off propagation delay tpdl drvl c load = 3 nf 15 tbd ns drvl turn?on propagation delay tpdh drvl c load = 3 nf 8.0 30 ns drvl pull down resistance drvl to pgnd, vcc = pgnd 37.5 k low side driver (vcc = 5 v) output impedance, sourcing current 2.5 output impedance, sinking current 1.0 drvl rise time tr drvl c load = 3 nf 30 ns drvl fall time tf drvl c load = 3 nf 22 ns drvl turn?off propagation delay tpdl drvl c load = 3 nf tbd ns drvl turn?on propagation delay tpdh drvl c load = 3 nf 12 ns drvl pull down resistance drvl to pgnd, vcc = pgnd 37.5 k en input input voltage high 2.0 v input voltage low 1.0 v hysteresis 500 mv normal mode bias current ?1 1 a enable pin sink current 4 30 ma propagation delay time pwm = 0 v, en going from 0 v to en hi to drvl rising to 10% 20 40 ns sw node sw node leakage current tbd a
NCP81155 www. onsemi.com 6 figure 2. gate timing diagram figure 3. pwm/en logic diagram pwm drvl drvh? sw tpdl drvl 90% tf drvl 10% 1v tpdh drvh 10% 90% tr drvh 1v 10% 90% 90% 10% tpdl drvh tf drvh tpdh drvl tr drvl pwm en drvh drvl tpd en_hi
NCP81155 www. onsemi.com 7 applications information the NCP81155 gate driver is a mosfet driver designed for driving two n?channel mosfets in a synchronous buck or buck?boost topology. low?side driver the low?side driver is designed to drive a ground referenced low r ds(on) n?channel mosfet. the voltage supply for the low?side driver is internally connected to the vcc and gnd pins. high?side driver the high?side driver is designed to drive a floating low r ds(on) n?channel mosfet. the gate voltage for the high?side driver is developed by a bootstrap circuit referenced to the sw pin. the bootstrap circuit is comprised of the integrated diode and an external bootstrap capacitor. when the NCP81155 is starting up, the sw pin is held at ground, allowing the bootstrap capacitor to charge up to vcc through the bootstrap diode. when the pwm input is driven high, the high?side driver will turn on the high?side mosfet using the stored charge of the bootstrap capacitor. as the high?side mosfet turns on, the sw pin rises. when the high?side mosfet is fully turned on, sw will settle to vin and bst will settle to vin + vcc (excluding parasitic ringing). bootstrap circuit the bootstrap circuit relies on an external charge storage capacitor (c bst ) and an integrated diode to provide current to the high?side driver. a multi?layer ceramic capacitor (mlcc) with a value greater than 100 nf should be used for c bst . power supply decoupling the NCP81155 can source and sink relatively large currents to the gate pins of the mosfets. in order to maintain a constant and stable supply voltage, a low?esr capacitor should be placed near the vcc and gnd pins. a mlcc between 1 f and 4.7 f is typically used. undervoltage lockout drvh and drvl are low until vcc reaches the vcc uvlo threshold, typically 4.35 v. once vcc reaches this threshold, the pwm signal will control drvh and drvl. there is a 200 mv hysteresis on vcc uvlo. there are pull?down resistors on drvh and drvl to prevent the gates of the mosfets from accumulating enough charge to turn on when the driver is powered off. bi?directional en signal the enable pin (en) is used to disable the drvh and drvl outputs to prevent power transfer. when en is above the en hi threshold, drvh and drvl change their states according to the pwm input. a uvlo fault turns on the internal mosfet that pulls the en pin towards ground. by connecting en to the dron pin of a controller, the controller is alerted when the driver encounters a fault condition. pwm input switching pwm between logic?high and logic?low states will allow the driver to operate in continuous conduction mode as long as vcc is greater than the uvlo threshold and en is high. the threshold limits are specified in the electrical characteristics table in this datasheet. refer to figure 2 for the gate timing diagrams. when pwm is set above pwm hi , drvl will first turn off after a propagation delay of tpdl drvl . to ensure non?overlap between drvl and drvh, there is a delay of tpdh drvh from the time drvl falls to 1 v, before drvh is allowed to turn on. when pwm falls below pwm lo , drvh will first turn off after a propagation delay of tpdl drvh . to ensure non?overlap between drvh and drvl, there is a delay of tpdh drvl from the time drvh ? sw falls to 1 v, before drvl is allowed to turn on. thermal considerations as power in the NCP81155 increases, it might become necessary to provide some thermal relief. the maximum power dissipation supported by the device is dependent upon board design and layout. mounting pad configuration on the pcb, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. when the NCP81155 has good thermal conductivity through the pcb, the junction temperature will be relatively low with high power applications. the maximum dissipation the NCP81155 can handle is given by: p d(max) [t j(max) t a ] r ja (eq. 1) since t j is not recommended to exceed 150 c, the NCP81155, soldered on to a 645 mm 2 copper area, using 1 oz. copper and fr4, can dissipate up to 2.3 w when the ambient temperature (t a ) is 25 c. the power dissipated by the NCP81155 can be calculated from the following equation: p d v cc [ n hs qg hs n ls qg ls f i standby ] (eq. 2) where n hs and n ls are the number of high?side and low?side fets, respectively, qg hs and qg ls are the gate charges of the high?side and low?side fets, respectively and f is the switching frequency of the converter.
NCP81155 www. onsemi.com 8 package dimensions dfn8 3x3, 0.5p case 506bj issue o ???? ???? ???? soldermask defined pin 1 reference a b c 0.10 2x 2x top view d e c 0.10 notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. e2 bottom view b 0.10 8x l 14 0.05 c ab c d2 e k 85 8x 8x (a3) c c 0.05 8x c 0.05 side view a1 a seating plane dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.64 1.84 e 3.00 bsc e2 1.35 1.55 e 0.50 bsc k 0.20 ??? l 0.30 0.50 note 3 l detail a optional construction l1 detail a 0.00 0.03 note 4 detail b 3.30 8x dimension: millimeters 0.63 1.55 1.85 0.50 pitch 8x 0.35 mounting footprint detail a on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent? marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or othe r applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death ma y occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidi aries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of per sonal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. sci llc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP81155/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your lo cal sales representative
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